SH7763 Datasheet, PDF (206/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.1.1 Address Spaces
Virtual Address Space: This LSI supports a 32-bit virtual address space, and can access a 4-
Gbyte address space. The virtual address space is divided into a number of areas, as shown in
figures 6.2 and 6.3. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be
accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. When the SQMD bit in
the MMU control register (MMUCR) is 0, a 64-Mbyte space in the store queue area can be
accessed. When the RMD bit in the on-chip memory control register (RAMCR) is 1, a 16-Mbyte
space in on-chip memory area can be accessed. Accessing areas other than the U0 area, store
queue area, and on-chip memory area in user mode will cause an address error.
When the AT bit in MMUCR is set to 1 and the MMU is enabled, the P0, P3, and U0 areas can be
mapped onto any physical address space in 1-, 4-, or 64-Kbyte, or 1-Mbyte page units. By using
an 8-bit address space identifier, the P0, P3, and U0 areas can be increased to a maximum of 256.
Mapping from the virtual address space to the 29-bit physical address space is carried out using
the TLB.
H'0000 0000
P0 area
Cacheable
Physical
address space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'0000 0000
U0 area
Cacheable
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P1 area
Cacheable
P2 area
Non-cacheable
P3 area
Cacheable
P4 area
Non-cacheable
Privileged mode
H'8000 0000
Address error
Store queue area ^{H'E000 0000}
Address error ^{H'E400 0000}
H'E500 0000
On-chip memory area _{H'E600 0000}
Address error _{H'FFFF FFFF}
User mode
Figure 6.2 Virtual Address Space (AT in MMUCR = 0)
Rev. 1.00 Oct. 01, 2007 Page 140 of 1956
REJ09B0256-0100