SH7763 Datasheet, PDF (1113/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.4.6 7-Bit Address Format
Figure 26.3 shows the format of data transfer from a master to a slave device (master data transmit
format). Figure 26.4 shows the data transfer format (master data receive format) when a master
device reads the second and the following byte data from a slave device.
S SLAVE ADDRESS R/W A
DATA
A
DATA
A/A P
0(Write)
: From MASTER to SLAVE
: From SLAVE to MASTER
Data transferres
(n Bytes + ACKNOWLEDGE)
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
S = Strat condition
P = Stop condition
Figure 26.3 Master Data Transmit Format
S SLAVE ADDRESS R/W A
DATA
A
DATA
A/A P
1(Read)
Data transferred
(n Bytes + ACKNOWLEDGE)
Figure 26.4 Master Data Receive Format
Figure 26.5 shows the combined format when the data transfer direction changes during one
transfer. When changing the direction after the first transfer, the repeated START condition (Sr),
slave address and R/W bits are transmitted. In this case, the R/W bit is set to the direction opposite
to the first transfer direction. The repeated START condition is issued by the master at the end of a
transmit or receive cycle if the enable start generation bit in the master control register has been
set.
Rev. 1.00 Oct. 01, 2007 Page 1047 of 1956
REJ09B0256-0100