SH7763 Datasheet, PDF (729/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
(2) Power-On Reset by Watchdog timer Overflowed in Sleep Mode
EXTAL
input
CLKOUT
output
WDT overflow
signal
STATUS[1:0]
output
HH (reset)
LL (normal)
WDT reset
stabilization time
WDT reset
holding time
Figure 17.7 STATUS Output by Watchdog timer overflow Power-On Reset
during Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 663 of 1956
REJ09B0256-0100