SH7763 Datasheet, PDF (328/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
11
IC111
0
10
IC110
0
9
IC109
0
8
IC108
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = LHLL (H'4).
R/W Clears masking of an
interrupt request when
IRL[7:4] = LHLH (H'5).
R/W Clears masking of an
interrupt request when
IRL[7:4] = LHHL (H'6).
R/W Clears masking of an
interrupt request when
IRL[7:4] = LHHH (H'7).
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
corresponding interrupt
mask (Interrupts are
enabled)
7
IC107
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HLLL (H'8).
6
IC106
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HLLH (H'9).
5
IC105
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HLHL (H'A).
4
IC104
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HLHH (H'B).
3
IC103
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HHLL (H'C).
2
IC102
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HHLH (H'D).
1
IC101
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = HHHL (H'E).
0
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 262 of 1956
REJ09B0256-0100