SH7763 Datasheet, PDF (689/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 External CPU Interface (EXCPU)
15.3 Register Descriptions
Table 15.2 shows the EXCPU register configuration. Table 15.3 shows the register states in each
operating mode.
Table 15.2 Register Configuration
Register Name
External CPU control register
External CPU memory space
select register
External CPU output interrupt
control register
Abbrevia-
tion
R/W
EXCCTRL R/W
EXCMSETR R/W
EXCINOR R/W
Area P4
Address
H'FE40 000C
H'FE40 0010
Area 7
Address
H'1E40 000C
H'1E40 0010
Access
Size
32
32
H'FE40 0014 H'1E40 0014 32
Table 15.3 Register States in Each Operating Mode
Register Name
External CPU control register
External CPU memory space
select register
External CPU output interrupt
control register
Abbrevia- Power-On Manual
tion
Reset
Reset
Sleep
EXCCTRL H'0000 0000 H'0000 0000 Retained
EXCMSETR H'0000 0000 H'0000 0000 Retained
Standby
Retained
Retained
EXCINOR H'0000 0000 H'0000 0000 Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 623 of 1956
REJ09B0256-0100