SH7763 Datasheet, PDF (1890/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 42 User Debugging Interface (H-UDI)
42.5.2 H-UDI Reset
A power-on reset is generated by the SDIR command. After the H-UDI reset assert command has
been sent from the H-UDI pin, sending the H-UDI reset negate command resets the CPU (see
figure 42.4). The required time between the H-UDI reset assert and H-UDI reset negate commands
is the same as the time for holding the reset pin low in order to reset this LSI by a power-on reset.
H-UDI pin
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Normal
Reset
Reset handling
Figure 42.4 H-UDI Reset
42.5.3 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting the appropriate command in SDIR
from the H-UDI. An H-UDI interrupt request signal is asserted when the INTREQ bit in SDINT is
set to 1 by setting the appropriate command. Since the interrupt request signal is not negated until
the INTREQ bit is cleared to 0 by software, it is not possible to lose the interrupt request. While an
H-UDI interrupt command is set in SDIR, SDINT is connected between the TDI and TDO pins.
42.6 Usage Notes
Once an SDIR command is set, it will be changed only by an assertion of the TRST signal,
making the TAP controller Test-Logic-Reset state, or writing other commands from the H-UDI.
The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when
using an emulator.
Rev. 1.00 Oct. 01, 2007 Page 1824 of 1956
REJ09B0256-0100