SH7763 Datasheet, PDF (1327/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
30.3.10 Serial Control 2 Register (SCSC2R)
SCSC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt
(RXI) requests.
Bit: 7
6
5
4
3
2
1
0
EIO ʵ
ʵ
ʵ
ʵ
ʵ
ʵ
ʵ
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
7
EIO
0
6 to 0 
All 0
R/W
R/W
R
Description
Error Interrupt Only
When the EIO bit is 1, even if the RIE bit is set to 1, a
receive data full interrupt (RXI) request is not sent to the
CPU. When the DMAC is used with this setting, the CPU
processes only ERI requests.
Receive data full interrupt (RXI) requests are determined
by the RIE bit setting.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1261 of 1956
REJ09B0256-0100