SH7763 Datasheet, PDF (1187/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.1 shows a block diagram of the SCIF/IrDA. Figures 28.2 to 28.4 show block diagrams
of the I/O ports in SCIF/IrDA.
Module data bus
SCIF2_RXD
SCIF2_TXD
SCIF2_SCK
SCSMRIR
Infrared data
communication
interface
Demodulation
unit
Modulation
unit
IrDA
BRGDL2
BRGCKS2
Baud rate generator
for external clock
(BRG)
SCFRDR2
16-stage
SCRSR2
[Legend]
SCRSR2: Receive shift register
SCFRDR2: Receive FIFO data register
SCTSR2: Transmit shift register
SCFTDR2: Transmit FIFO data register
SCSMR2: Serial mode register
SCSCR2: Serial control register
SCFSR2: Serial status register
SCFTDR2
16-stage
SCTSR2
SCSMR2
SCLSR2
SCTFDR2
SCRFDR2
SCFCR2
SCFSR2
SCSCR2
SCSPTR2
SCRER2
SCBRR2
Baud rate
generator
Transmit/
receive
control
Parity generation
Clock
Parity check
External clock
SCIF/IrDA
SCBRR2: Bit rate register
SCSPTR2: Serial port register
SCFCR2: FIFO control register
SCLSR2: Line status register
BRGDL2: BRG frequency division register
BRGCKS2: BRG clock select register
SCSMRIR: IrDA serial mode register
Figure 28.1 Block Diagram of SCIF/IrDA
Pck0
Pck0/4
Pck0/16
Pck0/64
TXI2
RXI2
ERI2
BRI2
Rev. 1.00 Oct. 01, 2007 Page 1121 of 1956
REJ09B0256-0100