SH7763 Datasheet, PDF (1294/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Table 29.11 Conditions to Issue Transmit Request
TFWM[2:0]
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Transmit Request
Empty area is 16 stages
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more
Used Areas
Smallest
Largest
Table 29.12 Conditions to Issue Receive Request
RFWM[2:0]
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Receive Request
Valid data is 1 stage or more
Valid data is 4 stages or more
Valid data is 8 stages or more
Valid data is 12 stages or more
Valid data is 16 stages
Used Areas
Smallest
Largest
The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the
FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data
area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled
when the above condition is not satisfied even if the FIFO is not empty or full.
(3) Number of FIFOs
The number of FIFO stages used in transmission and reception is indicated by the following
register.
• Transmit FIFO: The number of empty FIFO stages is indicated by the bits TFUA[4:0] in
SIFCTR.
• Receive FIFO: The number of valid data stages is indicated by the bits RFUA[4:0] in SIFCTR.
The above indicate possible data numbers that can be transferred by the CPU or DMAC.
Rev. 1.00 Oct. 01, 2007 Page 1228 of 1956
REJ09B0256-0100