SH7763 Datasheet, PDF (12/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

7.6.1 IC Address Array.................................................................................................. 206
7.6.2 IC Data Array ....................................................................................................... 208
7.6.3 OC Address Array ................................................................................................ 209
7.6.4 OC Data Array...................................................................................................... 210
7.7 Store Queues ...................................................................................................................... 212
7.7.1 SQ Configuration.................................................................................................. 212
7.7.2 Writing to SQ........................................................................................................ 212
7.7.3 Transfer to External Memory ............................................................................... 213
7.7.4 Determination of SQ Access Exception................................................................ 214
7.7.5 Reading from SQ .................................................................................................. 214
7.8 Notes on Using 32-Bit Address Extended Mode ............................................................... 215
Section 8 L Memory.......................................................................................... 217
8.1 Features.............................................................................................................................. 217
8.2 Register Descriptions......................................................................................................... 218
8.2.1 On-Chip Memory Control Register (RAMCR) .................................................... 220
8.2.2 L Memory Transfer Source Address Register 0 (LSA0) ...................................... 221
8.2.3 L Memory Transfer Source Address Register 1 (LSA1) ...................................... 223
8.2.4 L Memory Transfer Destination Address Register 0 (LDA0) .............................. 225
8.2.5 L Memory Transfer Destination Address Register 1 (LDA1) .............................. 227
8.3 Operation ........................................................................................................................... 229
8.3.1 Access from the CPU and FPU............................................................................. 229
8.3.2 Access from the SuperHyway Bus Master Module .............................................. 229
8.3.3 Block Transfer ...................................................................................................... 229
8.4 L Memory Protective Functions ........................................................................................ 231
8.5 Usage Notes ....................................................................................................................... 232
8.5.1 Page Conflict ........................................................................................................ 232
8.5.2 L Memory Coherency........................................................................................... 232
8.5.3 Sleep Mode ........................................................................................................... 232
8.6 Note on Using 32-Bit Address Extended Mode................................................................. 232
Section 9 Interrupt Controller (INTC)............................................................... 233
9.1 Features.............................................................................................................................. 233
9.1.1 Interrupt Method................................................................................................... 235
9.1.2 Interrupt Types in INTC ....................................................................................... 236
9.2 Input/Output Pins............................................................................................................... 240
9.3 Register Descriptions......................................................................................................... 241
9.3.1 Interrupt Control Register 0 (ICR0)...................................................................... 246
9.3.2 Interrupt Control Register 1 (ICR1)...................................................................... 248
9.3.3 Interrupt Priority Register (INTPRI) .................................................................... 249
Rev. 1.00 Oct. 01, 2007 Page xii of lxvi