SH7763 Datasheet, PDF (1219/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Table 28.7 SCSMR and SCSCR Settings for SCIF Clock Source Selection
SCSMR SCSCR Setting
Bit 7 Bit 1 Bit 0
C/A
CKE1 CKE0
0
0
0
1
1
0
1
1
1
0
0
1
Mode
Clock Source Description of SCK Pin
Asynchronous Internal clock The SCK pin is not used.
Pck0, Pck0/4,
Pck0/16,
Pck0/64
The SCK pin functions as an input
pin
(Input signals are ignored).
(Initial value)
The SCK pin outputs the clock
(with a frequency 16 times the bit
rate).
Input SC_CLK to The SCK pin inputs the clock
baud rate
(with a frequency 16 times the bit
generator for rate).
external clock
(SCIF_CLK,
Pck0) or SCK
(switched by
When SC_CLK is selected, the
SCK pin inputs the clock (Input
signals are ignored).
baud rate
Set the SCK input or SC_CLK so
generator's CKS ^{that the frequency of BRGCLK is}
register)
16 times the bit rate.
When selecting SC_CLK, set the
frequency of SC_CLK and DL, or
when selecting SCK, adjust the
frequency of the SCK input to
make the frequency of BRGCLK
16 times the bit rate.
Prohibited
—
—
Clock
synchronous
Internal clock
Pck0, Pck0/4,
Pck0/16,
Pck0/64
The SCK pin outputs the
synchronization clock.
The SCK pin outputs the
synchronization clock.
Rev. 1.00 Oct. 01, 2007 Page 1153 of 1956
REJ09B0256-0100