SH7763 Datasheet, PDF (1109/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 26.4 Suggested Settings for CDF and SCGD*
Peripheral Clock
Frequency
CDF
100 kHz
SCGD
66.7 MHz
3
19
Error
- 3.05 %
Note: * These are suggested values for the SCL rate.
Section 26 I²C Bus Interface (IIC)
CDF
3
- 5.26 %
400 kHz
SCGD
3
26.3.10 Receive and Transmit Data Registers (ICRXD and ICTXD)
Reading from or writing to these registers access different physical internal registers. When data is
to be transmitted, the contents of the shift register are loaded via TXD. After data has been
received into the shift register from the I²C bus, it is then loaded into RXD.
• Receive Data Register (ICRXD)
BIt:
Initial value:
R/W:
7
6
5
4
3
2
1
0
RXD[7:0]
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name Initial Value R/W
RXD[7:0] All 0
R
Description
Read—Receive Data
Data received by master or slave.
• Transmit Data Register (ICTXD)
BIt: 7
6
5
4
3
2
1
0
TXD[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: W W W W W W W W
Bit
7 to 0
Bit Name Initial Value R/W
TXD[7:0] All 0
W
Description
Write—Transmit Data
Data transmitted by master or slave.
Rev. 1.00 Oct. 01, 2007 Page 1043 of 1956
REJ09B0256-0100