SH7763 Datasheet, PDF (1461/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
Bit
10
9
8 to 6
5
4 to 0
Initial
Bit Name Value R/W Description
WMRT
0
W
HAC Warm Reset
Use a warm reset only after power-up, or only to exit
from the power-down mode by the power-down
command.
[Write]
0: Always write 0 to this bit before writing 1 again.
1: Performs a warm reset on the HAC.
[Read]
Always read as 0.

1
R
Reserved
Always 1 for read and write.

All 0 R
Reserved
Always 0 for read and write.
ST
0
W
Start Transfer
[Write]
1: Starts data transmission/reception.
0: Stops data transmission/reception at the end of the
current frame. Do not take this action to terminate
transmission/reception in normal operation.
[Read access]
Always read as 0.

All 0 R
Reserved
Always 0 for read and write.
To place the off-chip codec device into the power-down mode, write 1 to bit 12 of the register
index 26 in the off-chip codec via the HAC. When entering the power-down mode, the off-chip
codec stops HAC_BITCLK and suspends the normal operation. The off-chip codec acts in the
same manner at power-on. To resume the normal operation, perform a cold reset or a warm reset
on the off-chip codec.
Rev. 1.00 Oct. 01, 2007 Page 1395 of 1956
REJ09B0256-0100