SH7763 Datasheet, PDF (444/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Table 11.15 Relationship between Address and CE When Using PCMCIA Interface
Access
Read/ Size
Odd/
Bus (Bits) Write (bits)*¹ Even IOIS16 Access CE2 CE1 A0 D15 to D8
D7 to D0
8
Read 8
Even ×

1
0
0 Invalid
Read data
Odd ×

1
0
1 Invalid
Read data
16
Even ×
First
1
0
0 Invalid
Lower read data
Even ×
Second 1
0
1 Invalid
Upper read data
Odd ×





Write 8
Even ×

1
0
0 Invalid
Write data
Odd ×

1
0
1 Invalid
Write data
16
Even ×
First
1
0
0 Invalid
Lower write data
Even ×
Second 1
0
1 Invalid
Upper write data
Odd ×





16
Read 8
Even ×

1
0
0 Invalid
Read data
Odd ×

0
1
1 Read data
Invalid
16
Even ×

0
0
0 Upper read data Lower read data
Odd ×





Write 8
Even ×

1
0
0 Invalid
Write data
Odd ×

0
1
1 Write data
Invalid
16
Even ×

0
0
0 Upper write data Lower write data
Odd ×





Dynamic Read 8
Bus Sizing*²
Even 0

Odd 0

1
0
0 Invalid
Read data
0
1
1 Read data
Invalid
16
Even 0

0
0
0 Upper read data Lower read data
Odd 0





Write 8
Even 0

1
0
0 Invalid
Write data
Odd 0

0
1
1 Write data
Invalid
16
Even 0

0
0
0 Upper write data Lower write data
Odd 0





Read 8
Even 1

1
0
0 Invalid
Read data
Odd 1
First
0
1
1 Invalid
Invalid
Odd 1
Second 1
0
1 Invalid
Read data
16
Even 1
First
0
0
0 Invalid
Lower read data
Even 1
Second 1
0
1 Invalid
Upper read data
Odd 1





Rev. 1.00 Oct. 01, 2007 Page 378 of 1956
REJ09B0256-0100