SH7763 Datasheet, PDF (882/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.4 E-MAC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources
indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0











PFRO
IP
PHYIP
LCHN
GIP
MPDIP
ICDIP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
PFROIP 0
R/W PAUSE Frame Retransmit Interrupt Enable
0: Interrupt notification by the PFROI bit is disabled
1: Interrupt notification by the PFROI bit is enabled
3
PHYIP 0
R/W ET_PHY-INT Pin Interrupt Enable
0: Interrupt notification by the PHYI bit is disabled
1: Interrupt notification by the PHYI bit is enabled
2
LCHNGIP 0
R/W LINK Signal Change Interrupt Enable
0: Interrupt notification by the LCHNG bit is disabled
1: Interrupt notification by the LCHNG bit is enabled
1
MPDIP 0
R/W Magic Packet Detect Interrupt Enable
0: Interrupt notification by the MPD bit is disabled
1: Interrupt notification by the MPD bit is enabled
0
ICDIP
0
R/W Illegal Carrier Detect Interrupt Enable
0: Interrupt notification by the ICD bit is disabled
1: Interrupt notification by the ICD bit is enabled
Rev. 1.00 Oct. 01, 2007 Page 816 of 1956
REJ09B0256-0100