SH7763 Datasheet, PDF (298/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 L Memory
8.5 Usage Notes
8.5.1 Page Conflict
In the event of simultaneous access to the same page from different buses, page conflict occurs.
Although each access is completed correctly, this kind of conflict tends to lower L memory
accessibility. Therefore it is advisable to provide all possible preventative software measures. For
example, conflicts will not occur if each bus accesses different pages.
8.5.2 L Memory Coherency
In order to allocate instructions in the L memory, write an instruction to the L memory, execute
the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (L memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
8.5.3 Sleep Mode
The SuperHyway bus master module, such as DMAC, cannot access L memory in sleep mode.
8.6 Note on Using 32-Bit Address Extended Mode
In 32-bit address extended mode, L0SADR fields in LSA0, L1SADR fields in LSA1, L0DADR
fields in LDA0, and L1DADR fields in LDA1 are extended from 19-bit [28:10] to 22-bit [31:10].
Rev. 1.00 Oct. 01, 2007 Page 232 of 1956
REJ09B0256-0100