SH7763 Datasheet, PDF (1954/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.16 SIM Module Signal Timing
Table 43.29 SIM Module Signal Timing
Conditions:
V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
Symbol Min.
SIM_CLK clock cycle
t
SMCYC
2/t
Pcyc0
SIM_CLK clock high level width
t
SMCWH
0.4
×
t
SMCYC
SIM_CLK clock low level width
t
SMCWL
0.4
×
t
SMCYC
SIM_RST reset output delay
t
SMRD

Note: t_Pcyc0 is a cycle time of a peripheral clock (Pch0).
Max.
16/t
Pcyc0


20
Unit Figure
ns 43.66
ns
ns
ns
SIM_CLK
SIM_RST
t_SMCWH
t_SMCYC
t_SMCWL
t_SMRD
t_SMRD
Figure 43.66 SIM Module Signal Timing
Rev. 1.00 Oct. 01, 2007 Page 1888 of 1956
REJ09B0256-0100