SH7763 Datasheet, PDF (655/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 14.4 Transfer Request Sources
Peripheral
Module
CMT channel 0
CMT channel 1
CMT channel 2
CMT channel 3
CMT channel 4
SCIF0
SCIF1
SCIF2
HAC
USBF
SSI0
Setting Value for One
Channel (MID and RID)
H'03
H'07
H'0B
H'0F
H'13
H'21
H'22
H'29
H'2A
H'41
H'42
H'45
H'46
H'51
H'52
H'73
SSI1
H'77
SSI2
H'83
SSI3
H'87
MMCIF
H'93
SIM
H'A1
H'A2
Section 14 Direct Memory Access Controller (DMAC)
MID
RID
B'0000 00
B'11
B'0000 01
B'11
B'0000 10
B'11
B'0000 11
B'11
B'0001 00
B'11
B'0010 00
B'01
B'0010 00
B'10
B'0010 10
B'01
B'0010 10
B'10
B'0100 00
B'01
B'0100 00
B'10
B'0100 01
B'01
B'0100 01
B'10
B'0101 00
B'01
B'0101 00
B'10
B'0111 00
B'11
B'0111 01
B'11
B'1000 00
B'11
B'1000 01
B'11
B'10 01 00
B'11
B'1010 00
B'01
B'1010 00
B'10
Function





Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
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Transmit
Receive
Transmit and
Receive
Transmit and
Receive
Transmit and
Receive
Transmit and
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Transmit and
Receive
Transmit
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Rev. 1.00 Oct. 01, 2007 Page 589 of 1956
REJ09B0256-0100