SH7763 Datasheet, PDF (915/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.35 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0)
TSU_PRISL0 sets the priority control mode when the transmission request from the E-DMAC to
E-MAC-0 comes into collision with port 1 to 0 relay operations. This register must not be written
to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the
FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

PRIMD0[2:0]




PRISL0[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 15 
Initial
Value
All 0
14 to 12 PRIMD0[2:0] All 0
11 to 8 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W These bits set the priority control mode of E-MAC-0
transmission and port 1 to 0 relay operations.
H'0: Round robin
H'1: Transmission priority
H'2: Relay priority
H'4: Round robin, however switched to relay priority
when relay FIFO use amount exceeds the
PRISL0[7:0] setting
H'5: Transmission priority, however switched to relay
priority when relay FIFO use amount exceeds the
PRISL0[7:0] setting
Others: Setting prohibited
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 849 of 1956
REJ09B0256-0100