SH7763 Datasheet, PDF (1564/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3 Register Descriptions
Tables 36.2 (1) and (2) show the USBF register configuration when accessed in 8-bit units and 32-
bit units, respectively Table 36.3 shows the register state in each operating mode.
Table 36.2 (1) Register Configuration (Access Size = 8 bits)
Register Name
Abbreviation
Interrupt flag register 0
IFR0
Interrupt flag register 1
IFR1
Interrupt flag register 2
IFR2
Interrupt flag register 3
IFR3
Interrupt enable register 0 IER0
Interrupt enable register 1 IER1
Interrupt enable register 2 IER2
Interrupt enable register 3 IER3
Interrupt select register 0
ISR0
Interrupt select register 1
ISR1
Interrupt select register 2
ISR2
Interrupt select register 3
ISR3
EP0i data register
EPDR0i
EP0o data register
EPDR0o
EP0s data register
EPDR0s
EP1 data register
EPDR1
EP2 data register
EPDR2
EP3 data register
EPDR3
EP4 data register
EPDR4
EP5 data register
EPDR5
EP0o receive data size
register
EPSZ0o
EP1 receive data size register EPSZ1
EP4 receive data size register EPSZ4
Data status register
DASTS
Area P4
Address*
H'FFEC 0001
H'FFEC 0005
H'FFEC 0009
H'FFEC 000D
H'FFEC 0011
H'FFEC 0015
H'FFEC 0019
H'FFEC 001D
H'FFEC 0021
H'FFEC 0025
H'FFEC 0029
H'FFEC 002D
H'FFEC 0031
H'FFEC 0035
H'FFEC 0039
H'FFEC 0041
H'FFEC 0051
H'FFEC 0061
H'FFEC 0071
H'FFEC 0081
H'FFEC 0091
Area 7
Address*
H'1FEC 0001
H'1FEC 0005
H'1FEC 0009
H'1FEC 000D
H'1FEC 0011
H'1FEC 0015
H'1FEC 0019
H'1FEC 009D
H'1FEC 0021
H'1FEC 0025
H'1FEC 0029
H'1FEC 002D
H'1FEC 0031
H'1FEC 0035
H'1FEC 0039
H'1FEC 0041
H'1FEC 0051
H'1FEC 0061
H'1FEC 0071
H'1FEC 0081
H'1FEC 0091
Access size
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
H'FFEC 0095 H'1FEC 0095 8
H'FFEC 0099 H'1FEC 0099 8
H'FFEC 009D H'1FEC 009D 8
Rev. 1.00 Oct. 01, 2007 Page 1498 of 1956
REJ09B0256-0100