SH7763 Datasheet, PDF (1586/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.11 Interrupt Enable Register 0 (IER0)
IER0 enables the interrupt requests of the interrupt flag register 0. When an interrupt flag is set to
1 while the corresponding bit of each interrupt is set to 1, the INTN interrupt request (USBFI0 or
USBFI1) set in the ISR0 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
BRST EP1 EP2 EP2 SETUP EP0o EP0i EP0i
IE FULL IE TR IE EMPTY IE TS IE TS IE TR IE TS IE
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value R/W Description
31 to 8 
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
7
BRST IE
0
R/W BRST Interrupt Enable
6
EP1 FULL IE 0
R/W EP1 FULL Interrupt Enable
5
EP2 TR IE 0
R/W EP2 TR Interrupt Enable
4
EP2 EMPTY 0
IE
R/W EP2 EMPTY Interrupt Enable
3
SETUP TS IE 0
R/W SETUP TS Interrupt Enable
2
EP0o TS IE 0
R/W EP0o TS Interrupt Enable
1
EP0i TR IE 0
R/W EP0i TR Interrupt Enable
0
EP0i TS IE 0
R/W EP0i TS Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1520 of 1956
REJ09B0256-0100