SH7763 Datasheet, PDF (209/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
H'E000 0000
H'E400 0000
H'E500 0000
H'E600 0000
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
Store queue
Reserved area
On-chip memory area
Reserved area
Instruction cache address array
Instruction cache data array
Instruction TLB address array
Instruction TLB data array
Operand cache address array
Operand cache data array
Unified TLB and PMB address array
Unified TLB and PMB data array
Reserved area
H'FC00 0000
H'FFFF FFFF
Control register area
Figure 6.4 P4 Area
The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). In user mode, the access right is specified by the SQMD bit in MMUCR. For details, see
section 7.7, Store Queues.
The area from H'E500 0000 to H'E5FF FFFF comprises addresses for accessing the on-chip
memory. In user mode, the access right is specified by the RMD bit in RAMCR. For details, see
section 8, L Memory.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 7.6.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 7.6.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 6.6.1, ITLB Address Array.
The area from H'F300 0000 to H'F37F FFFF is used for direct access to instruction TLB data
array. For details, see section 6.6.2, ITLB Data Array.
Rev. 1.00 Oct. 01, 2007 Page 143 of 1956
REJ09B0256-0100