SH7763 Datasheet, PDF (1335/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
For the inverse-convention type, the logical level 1 is assigned to the A state, and the logical
level 0 to the Z state, and transmission and reception are performed in MSB-first. The data of
the start character shown in figure 30.3 is then H'3F. Even parity is used according to the smart
card specification, and so the parity bit is 0 corresponding to the Z state.
In addition, the only D7 to D0 bits are inverted by the SINV bit. The O/E bit in SCSMR is set to
odd parity mode to invert the parity bit. In transmission and reception, the setting condition is
similar.
(Z)
A Z Z A Z Z Z A A Z (Z) state
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(a) Direct converntion (SDIR = SINV = O/E = 0)
(Z)
A Z Z A A A A A A Z (Z) state
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
(b) Inverse convention (SDIR = SINV = O/E = 1)
Figure 30.3 Examples of Start Character Waveforms
30.4.4 Clocks
Only the internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock in the smart card interface. The bit rate is set using the bit rate register
(SCBRR) and the sampling register (SCSMPL), using the formula indicated below. Examples of
bit rates are listed in table 30.5
Here, when the CKE0 bit is set to 1 and the clock output is selected, a clock signal is output from
the SIM_CLK pin with frequency equal to (SCSMPL + 1) times the bit rate.
B = Pck0 × 10⁶ /{(S+1) × 2 (N+1)}
where
B = Bit rate (bits/s)
Pck0 = Peripheral clock0
S = SCSMPL setting (0 ≤ S ≤ 2047)
N = SCBRR setting (0 ≤ N ≤ 7).
Rev. 1.00 Oct. 01, 2007 Page 1269 of 1956
REJ09B0256-0100