SH7763 Datasheet, PDF (1384/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.16 Data Register (DR)
DR is a register to read/write the FIFO data.
Word- or byte-access is possible.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: —
R/W: R/W
DR
———————————————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
(7 to 0)
Bit Name
DR
Initial
Value R/W
Undefined R/W
Description
Register to read/write FIFO data.
Word- or byte-access is possible.
However, address 2n + 1 cannot be accessed in bytes.
31.3.17 FIFO Pointer Clear Register (FIFOCLR)
The FIFO write/read pointer is cleared by writing an arbitrary value to FIFOCLR.
Bit: 7
6
5
4
3
2
1
0
FIFOCLR
Initial value: — — — — — — — —
R/W: W W W W W W W W
Bit
7 to 0
Bit Name
FIFOCLR
Initial
Value R/W
Undefined W
Description
The FIFO pointer is cleared by writing an arbitrary value
to this register.
Rev. 1.00 Oct. 01, 2007 Page 1318 of 1956
REJ09B0256-0100