SH7763 Datasheet, PDF (1175/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
(5) Serial Data Reception (Clocked Synchronous Mode)
Figure 27.19 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to clocked synchronous mode
without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags
are cleared to 0.
Initialization
[1]
[1] SCIF initialization:
See Sample SCIF Initialization
Flowchart in figure 27.16.
Start of reception
[2] Receive error handling:
Read ORER flag in SCLSR
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be
resumed while the ORER flag is set
ORER = 1?
Yes
to 1.
[2]
[3] SCIF status check and receive data
No
Error handling
read:
Read SCFSR and check that RDF =
Read RDF flag in SCFSR
[3]
1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
No
RDF = 1?
0 to 1 can also be identified by an
RXI interrupt.
Yes
Read receive data in
SCFRDR, and clear RDF
[4]
flag in SCFSR to 0
No
All data received?
Yes
[4] Serial reception continuation
procedure:
To continue serial reception, read at
least the receive trigger set number
of receive data bytes from SCFRDR,
read 1 from the RDF flag, then clear
the RDF flag to 0. The number of
receive data bytes in SCFRDR can
be ascertained by reading SCFRDR.
Clear RE bit in SCSCR to 0
End of reception
Figure 27.19 Sample Serial Reception Flowchart (1)
Rev. 1.00 Oct. 01, 2007 Page 1109 of 1956
REJ09B0256-0100