SH7763 Datasheet, PDF (1795/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.24 Port I Data Register (PIDR)
PIDR is an 8-bit readable/writable register that stores port I data.
Bit: 7
6
5
4
3
2
1
0
PI7DT PI6DT PI5DT PI4DT PI3DT PI2DT PI1DT PI0DT
Initial value: 0
R/W: R
0 Pin state Pin state Pin state Pin state 0
0
R R/W R/W R
R R/W R/W
Initial
Bit
Bit Name value R/W Description
7
PI7DT
0
R
Each of these bits stores output data for the
6
PI6DT
0
R
corresponding pin that is used as a general output port.
If the port is read, the value of the corresponding bit in
5
PI5DT
Pin state R/W _{this register will be read for a pin configured as a}
4
PI4DT
Pin state R/W ^{general output port, while the state of the corresponding}
pin will be read for a pin configured as a general input
3
PI3DT
Pin state R
port.
2
PI2DT
Pin state R
1
PI1DT
0
R/W
0
PI0DT
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 1729 of 1956
REJ09B0256-0100