SH7763 Datasheet, PDF (676/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
14.4.7 DREQ Pin Sampling Timing
Figures 14.13 to 14.16 show the sample timing of the DREQ input in each bus mode, respectively.
CKOUT
Bus cycle
DREQ
(Rising edge)
DRAK
(Low-active)
DACK
(Low-active)
CPU
1st acceptance
DMAC
CPU
2nd acceptance
: Non-sensitive period
Acceptance
started
Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CLKOUT
Bus cycle
DREQ
(Overrun 0,
Low-level)
DRAK
(Low-active)
DACK
(Low-active)
CPU
1st acceptance
DMAC
CPU
2nd acceptance
Acceptance started
CLKOUT
Bus cycle
DREQ
(Overrun 1,
Low-level)
DRAK
(Low-active)
DACK
(Low-active)
CPU
1st acceptance
DMAC
CPU
2nd acceptance
: Non-sensitive period
Acceptance started
Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev. 1.00 Oct. 01, 2007 Page 610 of 1956
REJ09B0256-0100