SH7763 Datasheet, PDF (405/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value
16
DMABST 0
15

0
14
HIZCNT 0
13 to 7 
0
6 to 0 ASYNC[6:0] All 0
Section 11 Local Bus State Controller (LBSC)
R/W Description
R/W DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by the
DMAC. When this bit is cleared to 0, the priority is as
follows: bus release, DMAC, CPU. When this bit is set
to 1, the bus release is not performed until the
completion of the DMAC burst transfer. This bit is
initialized at a power-on reset.
0: DMAC burst mode transfer priority setting off
1: DMAC burst mode transfer priority setting on
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W High Impedance (Hi-Z) Control
Specifies the state of signals WEn and RD/FRAME
during the software standby mode and the bus-released
state.
0: Signals of WEn and RD/FRAME are high-impedance
during the bus-released state
1: Signals of WEn and RD/FRAME are output during
the bus-released state
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Asynchronous Input
Enable asynchronous input to the corresponding pins.
0: Input signals to the corresponding pins are
synchronized with CLKOUT
1: Input signals to the corresponding pins are
asynchronous to CLKOUT
ASYNC[6]: DREQ3
ASYNC[5]: DREQ2
ASYNC[4]: DREQ1
ASYNC[3]: DREQ0
ASYNC[2]: IOIS16
ASYNC[1]: BREQ
ASYNC[0]: RDY
Rev. 1.00 Oct. 01, 2007 Page 339 of 1956
REJ09B0256-0100