SH7763 Datasheet, PDF (443/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Specify the number of wait cycles between accesses to be 0 for the DACK assertion area, when
setting the size of DMA transfer is 16-byte. After the DMA burst transfer has finished, that
DACKBST was enabled, set the DACKBST bit to 1 again before starting the next DMA transfer.
(a) IO Card Interface DACKBST Invalid
CExx
DACK
(b) ATA Complement Mode DACKBST Valid
CExx
DACK
Note: Number of DMA transter times: 4,DMA transter size: word (16-bit)
Figure 11.14 CExx and DACK Output of ATA Complete Mode in DMA Transfer
Rev. 1.00 Oct. 01, 2007 Page 377 of 1956
REJ09B0256-0100