SH7763 Datasheet, PDF (201/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
5.7 Usage Notes
(1) Return from exception handling
1. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the
BL bit in SR to 1 before restoring them.
2. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR
contents are saved in SR, and branch is made to the SPC address to return from the exception
handling routine.
(2) If an exception or interrupt occurs when BL bit in SR = 1
1. Exception
When an exception other than a user break occurs, a manual reset is executed. The value in
EXPEVT at this time is H'00000020; the SPC and SSR contents are undefined.
2. Interrupt
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the
BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can
be held pending or accepted according to the setting made by software.
In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set to 1.
(3) SPC when an exception occurs
1. Re-execution type exception
The PC value for the instruction at which the exception occurred is set in SPC, and the
instruction is re-executed after returning from the exception handling routine. If an exception
occurs in a delay slot instruction, however, the PC value for the delayed branch instruction is
saved in SPC regardless of whether or not the preceding delay slot instruction condition is
satisfied.
2. Completion type exception or interrupt
The PC value for the instruction following that at which the exception occurred is set in SPC.
If an exception occurs in a branch instruction with delay slot, however, the PC value for the
branch destination is saved in SPC.
(4) RTE instruction delay slot
1. The instruction in the delay slot of the RTE instruction is executed only after the value saved
in SSR has been restored to SR. The acceptance of the exception related to the instruction
access is determined depending on SR before restoring, while the acceptance of other
exceptions is determined depending on the processing mode by SR after restoring or the BL
Rev. 1.00 Oct. 01, 2007 Page 135 of 1956
REJ09B0256-0100