SH7763 Datasheet, PDF (1687/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
37.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR)
LDUINTLNR sets the point where the user specified interrupt is generated. Setting is done in
horizontal line units.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





UINTLN[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value R/W Description
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 UINTLN
[10:0]
00001001111 R/W
User Specified Interrupt Generation Line Number
Specifies the line in which the user specified
interrupt is generated (line units).
Set (the number of lines in which interrupts are
generated) −1
Example: Generate the user specified interrupt in
the 80th line.
UINTLN = 160/2 − 1 = 79 = H'04F
Notes: 1. When using the LCD module with STN/TFT display, the setting value of this register
should be equal to lower than the vertical display line number (VDLN) in LDVDLNR.
2. When using the LCD module with DSTN display, the setting value of this register should
be equal to or lower than half the vertical display line number (VDLN) in LDVDLNR. The
user specified interrupt is generated at the point when the LCDC read the specified
piece of image data in lower display from VRAM.
Rev. 1.00 Oct. 01, 2007 Page 1621 of 1956
REJ09B0256-0100