SH7763 Datasheet, PDF (533/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(5) PCI Revision ID Register (PCIRID)
This register specifies a device specific revision identifier.
Bit: 7
6
5
4
3
2
1
0
RID
Initial value: 0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R
PCI R/W: R R R R R R R R
Bit
7 to 0
Bit Name
RID
Initial
Value
H'00
R/W
SH: R
PCI: R
Description
Revision ID
Indicates the PCIC revision.The initial value is
H'00.RID value varies according to the logic version of
the PCIC and it may be changed in the future.
(6) PCI Program Interface Register (PCIPIF)
This register is the programming interface for the IDE controller class code. For details of the
class code, refer to “PCI Local Bus Specification Revision 2.2 Appendix D.”
Bit: 7
6
5
4
3
2
1
0
MIDED — — — PIS OMS PIP OMP
Initial value: 0
0
0
0
0
0
0
0
SH R/W: R/W R R R R/W R/W R/W R/W
PCI R/W: R R R R R R R R
Initial
Bit
Bit Name Value R/W
Description
7
MIDED 0
SH: R/W PCI Master IDE Device
PCI: R
Specifies the PCI master IDE device.
1: PCI master IDE device
0: PCI slave IDE device
When the CFINIT bit in PCICR is 0, this bit is writable.
When the CFINIT bit in PCICR is 1, writing is ignored.
This bit is readable.
Rev. 1.00 Oct. 01, 2007 Page 467 of 1956
REJ09B0256-0100