SH7763 Datasheet, PDF (1263/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
9
TXE
0
R/W Transmit Enable
0: Disables data transmission from the SIOF_TXD pin
1: Enables data transmission from the SIOF_TXD pin
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according
to the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOF_TXD pin
begins.
This bit is initialized upon a transmit reset.
8
RXE
0
R/W Receive Enable
0: Disables data reception from SIOF_RXD
1: Enables data reception from SIOF_RXD
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOF_RXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
This bit is initialized upon receive reset.
Rev. 1.00 Oct. 01, 2007 Page 1197 of 1956
REJ09B0256-0100