SH7763 Datasheet, PDF (1100/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.3.3 Slave Interrupt Enable Register (ICSIER)
BIt: 7
6
5
4
3
2
1
0
−
−
− _{SSRE SDEE SDTE SDRE SARE}
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W
Bit
7 to 5
4
3
2
1
0
Bit Name
—
Initial Value R/W
All 0
R
SSRE
0
R/W
SDEE
0
R/W
SDTE
0
R/W
SDRE
0
R/W
SARE
0
R/W
Description
Reserved
The write value should always be 0.
Slave Stop Received Interrupt Enable
0: Disables the SSR interrupt.
1: Enables the SSR interrupt.
Slave Data Empty Interrupt Enable
0: Disables the SDE interrupt.
1: Enables the SDE interrupt.
Slave Data Transmitted Interrupt Enable
0: Disables the SDT interrupt.
1: Enables the SDT interrupt.
Slave Data Received Interrupt Enable
0: Disables the SDR interrupt.
1: Enables the SDR interrupt.
Slave Address Received Interrupt Enable
0: Disables the SAR interrupt.
1: Enables the SAR interrupt.
Rev. 1.00 Oct. 01, 2007 Page 1034 of 1956
REJ09B0256-0100