SH7763 Datasheet, PDF (215/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.2.3 Translation Table Base Register (TTB)
TTB is used to store the base address of the currently used page table, and so on. The contents of
TTB are not changed unless a software directive is issued. This register can be used freely by
software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTB
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TTB
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
6.2.4 TLB Exception Address Register (TEA)
After an MMU exception or address error exception occurs, the virtual address at which the
exception occurred is stored. The contents of this register can be changed by software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEA
Virtual address at which MMU exception or address error occurred
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
Initial value:
R/W: R/W
14
TEA
R/W
13 12 11 10 9
8
7
6
5
4
3
Virtual address at which MMU exception or address error occurred
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2
R/W
1
R/W
0
R/W
6.2.5 MMU Control Register (MMUCR)
The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should
be performed by a program in the P1 or P2 area.
After MMUCR has been updated, execute one of the following three methods before an access
(including an instruction fetch) to the P0, P3, U0, or store queue area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0,
P3, or U0 area.
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating MMUCR, the specific instruction
does not need to be executed. However, note that the CPU processing performance will be
lowered because the instruction fetch is performed again for the next instruction after
MMUCR has been updated.
Rev. 1.00 Oct. 01, 2007 Page 149 of 1956
REJ09B0256-0100