SH7763 Datasheet, PDF (1727/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
Bit Bit Name
13 ADST
12 to 8 
Initial Value R/W
0
R/W
All 0
R
Description
A/D Start
Starts or stops A/D conversion. The ADST bit remains
set to 1 during A/D conversion.
0: A/D conversion is stopped
1: Single mode: A/D conversion starts. This bit is
cleared to 0 automatically when conversion on the
specified channel ends. Even when the ADST bit is
cleared to 0 (by software), A/D conversion does not
stop (0 cannot be written to this bit during A/D
conversion).
Multi mode: A/D conversion starts. This bit is cleared
to 0 automatically when conversion on the specified
channels has been performed for one cycle. When
the ADST bit is cleared to 0 (by software), A/D
conversion stops when the currently executed
channel ends.
Scan mode: A/D conversion starts. A/D conversion
continues until the ADST bit is cleared to 0 by
software, a reset, or a transition to standby mode.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1661 of 1956
REJ09B0256-0100