SH7763 Datasheet, PDF (1093/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
Channel Register Name
Abbreviation R/W
Area P4
Area 7
Access
Address*¹ Address*¹ Size
1
Slave control register 1 ICSCR1
R/W H'FFE7 8000 H'1FF7 8000 8
Master control register 1 ICMCR1 R/W H'FFE7 8004 H'1FF7 8004 8
Slave status register 1
Master status register 1
ICSSR1
ICMSR1
R/(W)*² H'FFE7 8008 H'1FF7 8008 8
R/(W)*³ H'FFE7 800C H'1FF7 800C 8
Slave interrupt enable
register 1
ICSIER1
R/W H'FFE7 8010 H'1FF7 8010 8
Master interrupt enable ICMIER1
register 1
R/W
H'FFE7 8014 H'1FF7 8014 8
Clock control register 1 ICCCR1 R/W H'FFE7 8018 H'1FF7 8018 8
Slave address register 1 ICSAR1
R/W H'FFE7 801C H'1FF7 801C 8
Master address register 1 ICMAR1 R/W H'FFE7 8020 H'1FF7 8020 8
Receive data register 1 ICRXD1
R/W H'FFE7 8024 H'1FF7 8024 8
Transmit data register 1 ICTXD1
R/W H'FFE7 8024 H'1FF7 8024 8
Notes: 1. P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
2. Only 0 can be written to bits 4 to 0 to clear the flags.
3. Only 0 can be written to bits 6 to 0 to clear the flags.
Rev. 1.00 Oct. 01, 2007 Page 1027 of 1956
REJ09B0256-0100