SH7763 Datasheet, PDF (536/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(9) PCI Cacheline Size Register (PCICLS)
Bit: 7
6
5
4
3
2
1
0
CLS
Initial value: 0
0
1
0
0
0
0
0
SH R/W: R R R R R R R R
PCI R/W: R R R R R R R R
Bit
7 to 0
Bit Name
CLS
Initial
Value
H'20
R/W
SH: R
PCI: R
Description
Cache Line Size: Not supported
A memory target does not support a cache. SDON
and SBO are ignored.
(10) PCI Latency Timer Register (PCILTM)
This register specifies, in units of PCI bus clocks, the value of latency timer for this PCI bus
master.
Bit:
Initial value:
SH R/W:
PCI R/W:
7
0
R/W
R/W
6
0
R/W
R/W
5
0
R/W
R/W
4
3
LTM
0
0
R/W R/W
R/W R/W
2
0
R/W
R/W
1
0
R/W
R/W
0
0
R/W
R/W
Bit
7 to 0
Bit Name
LTM
Initial
Value
H'00
R/W
SH: R/W
PCI: R/W
Description
PCI Latency Timer
Specifies the maximum number of acquisition clocks
of PCI bus when the PCIC is operating as the master.
Rev. 1.00 Oct. 01, 2007 Page 470 of 1956
REJ09B0256-0100