SH7763 Datasheet, PDF (320/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.7 Interrupt mask register 2 (INTMSK2)
INTMSK2 is 32-bit readable and writable with conditions registers that control mask settings for
each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits
in INTMSKCLR2. Writing 0 to bits in INTMSK2 is invalid.
INTMSK2 is valid when an IRL interrupt, which is generated by encoding input signals on pins
IRL7 to IRL4 or IRL3 to IRL0, is requested while an IRL interrupt is not masked by INTMSK1.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− ^{IM015 IM014 IM013 IM012 IM011 IM010 IM009 IM008 IM007 IM006 IM005 IM004 IM003 IM002 IM001}
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− ^{IM115 IM114 IM113 IM112 IM111 IM110 IM109 IM108 IM107 IM106 IM105 IM104 IM103 IM102 IM101}
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Bit Name Value R/W Description
31
IM015
0
30
IM014
0
R/W Sets masking of an
interrupt request when
IRL [3:0] = LLLL (H'0).
R/W Sets masking of an
interrupt request when
IRL [3:0] = LLLH (H'1).
[When reading]
0: Interrupts are accepted
1: Interrupts are masked
[When writing]
0: Invalid
29
IM013
0
R/W Sets masking of an
interrupt request when
IRL [3:0] = LLHL (H'2).
1: Interrupts are masked
28
IM012
0
R/W Sets masking of an
interrupt request when
IRL [3:0] = LLHH (H'3).
27
IM011
0
R/W Sets masking of an
interrupt request when
IRL [3:0] = LHLL (H'4)..
26
IM010
0
R/W Sets masking of an
interrupt request when
IRL [3:0] = LHLH (H'5).
Rev. 1.00 Oct. 01, 2007 Page 254 of 1956
REJ09B0256-0100