SH7763 Datasheet, PDF (494/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.3 shows the relationship between write values in SDMR and output signals to the
memory pins.
SDRAM ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
address ^{1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0}
L: Low level
H: High level
M_CS
M_RAS
M_CAS
M_WE
DDR-SDRAM
H
L
L
L
L
H
H
L
L
L
L
L
L
L
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
L
L
BA0
BA1
L
L
L
CS
RAS
CAS
L _WE
Figure 12.3 Relationship between Write Values in SDMR and
Output Signals to Memory Pins
For example, when the DLL reset release, CAS latency of 2.5 cycles, sequential burst sequence,
and burst length of 2 are set to the mode register in the DDR-SDRAM, the following signals must
be output to the DDR-SDRAM pins.
CS = low, RAS = low, CAS = low, WE = low, BA0 = low, BA1 = low,
MA13/MA12/MA11/MA10/MA9 = low, MA8 = low, MA7 = low, MA6 = high, MA5 = high,
MA4 = low, MA3 = low, MA2 = low, MA1 = low, and MA0 = high
To output the above control signals, write access to address H'FE90 0308 in SDMR is made in
longwords. Then the above control signals are output to the DDR-SDRAM pins. Write data to
SDMR is Don't care.
Rev. 1.00 Oct. 01, 2007 Page 428 of 1956
REJ09B0256-0100