SH7763 Datasheet, PDF (412/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
11.4.4 CSn Wait Control Register (CSnWCR)
The CSn wait control register (CSnWCR) is a 32-bit readable/writable register that specifies the
number of wait cycles to be inserted, the pitch of data access for burst memory accesses, and the
number of cycles to be inserted for the address setup time to the read/write strobe assertion or for
the data hold time from the write strobe negation.
This allows direct connection of even low-speed memories without an external circuit.
CSnBCR is initialized to H'7777 770F by a power-on reset or a manual reset.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−
ADS
−
ADH
−
RDS
−
RDH
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−
WTS
−
WTH
−
BSH
IW[3:0]
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
30 to 28 ADS
111
R/W Address Setup Cycle
Specify the number of cycles to be inserted to ensure
the address setup time to the CSn assertion. (Available
only when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 346 of 1956
REJ09B0256-0100