SH7763 Datasheet, PDF (1838/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
0
BIE
0
R/W Break Enable
Specifies whether or not to request a break when the
match condition is satisfied for the channel.
0: Does not request a break.
1: Requests a break.
41.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)
CAR0 and CAR1 are readable/writable 32-bit registers specifying the virtual address to be
included in the break conditions for channels 0 and 1, respectively.
• CAR0
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CA
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CA
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value
R/W Description
CA
Undefined R/W Compare Address
Specifies the address to be included in the break
conditions.
When the operand bus has been specified using the
CBR0 register, specify the SAB address in CA[31:0].
Rev. 1.00 Oct. 01, 2007 Page 1772 of 1956
REJ09B0256-0100