SH7763 Datasheet, PDF (803/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 16-Bit Timer Pulse Unit (TPU)
20.4.4 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, or 1, output can be selected
as the output level in response to compare match of each TGRA.
Designating TGRB compare match as the counter clearing source enables the period to be set in
that register. All channels can be designated for PWM mode independently.
PWM output is generated from the TPU_TO pin using TGRB as the period register and TGRA as
duty registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a period register compare match, the output value of each pin is the initial
value set in TIOR. Set TIOR so that the initial output and an output value by compare match are
different. If the same levels or toggle outputs are selected, operation is disabled.
Conditions of duty 0% and 100% are shown below.
• Duty 0% : The set value of the period register (TGRB) is TGRA + 1 for the duty register
(TGRA).
• Duty 100% : The set value of the duty register (TGRA) is 0.
In PWM mode 1, a maximum 4-phase PWM output is possible.
Rev. 1.00 Oct. 01, 2007 Page 737 of 1956
REJ09B0256-0100