SH7763 Datasheet, PDF (1014/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Bit
Initial
Bit
Name Value R/W Description
29, 28 RFP[1:0] 00
R/W Receive Frame Position 1, 0
The E-DMAC indicates by write-back operation whether
information of the corresponding descriptor represents
information about the start, middle, or end of the receive
frame.
00: The information of the descriptor represents information
about the middle of the frame
01: The information of the descriptor represents information
about the end of the frame
10: The information of the descriptor represents information
about the start of the frame
11: The information of the descriptor represents all
information about the frame (single-frame/single-
descriptor (single-buffer))
Reference
The relationship between a frame after reception of one
frame and a descriptor is described below.
• For single-frame/single-descriptor operation
First descriptor: RFP[1:0] = 11
• For single-frame/two-descriptor operation
First descriptor: RFP[1:0] = 10
Second descriptor: RFP[1:0] = 01
• For single-frame/three-descriptor operation
First descriptor: RFP[1:0] = 10
Second descriptor: RFP[1:0] = 00
Third descriptor: RFP[1:0] = 01
When the number of divisions is large, a descriptor row is
configured by adding intermediate descriptors with RFP[1:0]
= 00.
27
RFE
0
R/W Receive Frame Error Occurrence
Indicates that an error occurred in the receive frame.
0: RFS11 to RFS0 are all 0
1: One of RFS11 to RFS0 is 0
Each of RFS8 to RFS0 can be masked by using TRSCER.
RFS11 to RFS9 cannot be masked.
This bit is set by the E-DMAC write-back operation.
Rev. 1.00 Oct. 01, 2007 Page 948 of 1956
REJ09B0256-0100