SH7763 Datasheet, PDF (1382/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.14 Transfer Clock Control Register (CLKON)
CLKON controls the transfer clock frequency and clock ON/OFF.
Bits CSEL[3:0] must be set to 0001 for the peripheral clock of 33.3 MHz in order to achieve a
16.7-Mbps transfer clock in the MMCIF. At this time, use a sufficiently slow clock for transfer in
open-drain type output in MMC mode.
In a command sequence, do not perform clock ON/OFF or frequency modification.
Bit: 7
6
5
4
3
2
1
0
CLKON — — —
CSEL[3:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R
R R/W R/W R/W R/W
Bit
7
6 to 4
3 to 0
Initial
Bit Name Value R/W
CLKON
0
R/W
—
All 0 R
CSEL[3:0] 0000 R/W
Description
Clock On
0: Fixes the transfer clock output from the MMC_CLK
pin to low level.
1: Outputs the transfer clock from the MMC_CLK pin.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Frequency Select
0000: Setting prohibited
0001: Uses the 1/2-divided system clock as a transfer clock.
0010: Uses the 1/4-divided system clock as a transfer clock.
0011: Uses the 1/8-divided system clock as a transfer clock.
0100: Uses the 1/16-divided system clock as a transfer clock.
0101: Uses the 1/32-divided system clock as a transfer clock.
0110: Uses the 1/64-divided system clock as a transfer clock.
0111: Uses the 1/128-divided system clock as a transfer clock.
1000: Uses the 1/256-divided system clock as a transfer clock.
1001 to 1111: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1316 of 1956
REJ09B0256-0100