SH7763 Datasheet, PDF (17/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 External CPU Interface (EXCPU) ...................................................621
15.1 Features.............................................................................................................................. 621
15.2 Input/Output Pins ............................................................................................................... 622
15.3 Register Descriptions ......................................................................................................... 623
15.3.1 External CPU Control Register (EXCCTRL) ....................................................... 624
15.3.2 External CPU Memory Space Select Register (EXCMSETR) ............................. 625
15.3.3 External CPU Interrupt Output Control Register (EXCINOR)............................. 626
15.4 Operation ........................................................................................................................... 627
Section 16 Clock Pulse Generator (CPG)..........................................................633
16.1 Features.............................................................................................................................. 633
16.2 Input/Output Pins ............................................................................................................... 636
16.3 Clock Operating Mode....................................................................................................... 637
16.4 Register Descriptions ......................................................................................................... 638
16.4.1 Frequency Control Register (FRQCR) ................................................................. 639
16.4.2 PLL Control Register (PLLCR)............................................................................ 641
16.5 Notes on Board Design ...................................................................................................... 642
Section 17 Watchdog Timer and Reset (WDT).................................................645
17.1 Features.............................................................................................................................. 645
17.2 Input/Output Pins ............................................................................................................... 647
17.3 Register Descriptions ......................................................................................................... 648
17.3.1 Watchdog Timer Stop Time Register (WDTST) .................................................. 649
17.3.2 Watchdog Timer Control/Status Register (WDTCSR)......................................... 650
17.3.3 Watchdog timer Base Stop Time Register (WDTBST) ........................................ 652
17.3.4 Watchdog Timer Counter (WDTCNT)................................................................. 653
17.3.5 Watchdog Timer Base Counter (WDTBCNT) ..................................................... 653
17.4 Operation ........................................................................................................................... 654
17.4.1 Reset request......................................................................................................... 654
17.4.2 Using watchdog timer mode ................................................................................. 655
17.4.3 Using Interval timer mode .................................................................................... 656
17.4.4 Time for WDT Overflow ...................................................................................... 656
17.4.5 Clearing WDT Counter......................................................................................... 658
17.5 Status Pin Change Timing during Reset ............................................................................ 659
17.5.1 Power-On Reset by PRESET................................................................................ 659
17.5.2 Power-On Reset by Watchdog Timer Overflow................................................... 662
17.5.3 Manual Reset by Watchdog Timer Overflow ....................................................... 664
Rev. 1.00 Oct. 01, 2007 Page xvii of lxvi