SH7763 Datasheet, PDF (554/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
1
RSTCTL 0
SH: R/W PCIRESET Output
PCI: R
Controls the PCIRESET output by software. This bit is
valid when the PCIC operates in host bus bridge
mode.
0: Negates PCIRESET output (high level output)
1: Asserts PCIRESET output (low level output)
Note: The PCIRESET is also asserted during power-
on reset.
0
CFINIT 0
SH: R/W PCI Internal Register Initialize Control
PCI: R
Set this bit to 1 after the initialization of the PCIC
internal registers are completed. Setting this bit
enables accesses from the PCI bus. During
initialization in host bus bridge mode, the bus is not
given to the device on the PCI bus. In normal mode,
the PCIC returns RETRY when it is accessed from the
PCI bus.
0: During initialization
1: Initialization completed
(2) PCI Local Space Register 0 (PCILSR0)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———
LSR
————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MBA
RE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R/W
PCI R/W: R R R R R R R R R R R R R R R R
Rev. 1.00 Oct. 01, 2007 Page 488 of 1956
REJ09B0256-0100