SH7763 Datasheet, PDF (245/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.7.3 Privileged Space Mapping Buffer (PMB) Configuration
In 32-bit address extended mode, virtual addresses in the P1 or P2 area are translated according to
the PMB mapping information. The PMB has 16 entries and configuration of each entry is as
follows.
Entry 0
Entry 1
Entry 2
VPN [31:24] V
VPN [31:24] V
VPN [31:24] V
PPN [31:24]
PPN [31:24]
PPN [31:24]
SZ [1:0] C UB WT
SZ [1:0] C UB WT
SZ [1:0] C UB WT
Entry 15 VPN [31:24] V
PPN [31:24] SZ [1:0] C UB WT
Figure 6.17 PMB Configuration
[Legend]
• VPN: Virtual page number
For 16-Mbyte page: Upper 8 bits of virtual address
For 64-Mbyte page: Upper 6 bits of virtual address
For 128-Mbyte page: Upper 5 bits of virtual address
For 512-Mbyte page: Upper 3 bits of virtual address
Note: B'10 should be set to the upper 2 bits of VPN in order to indicate P1 or P2 area.
• SZ: Page size bits
Specify the page size.
00: 16-Mbyte page
01: 64-Mbyte page
10: 128-Mbyte page
11: 512-Mbyte page
• V: Validity bit
Indicates whether the entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset.
Not affected by a manual reset.
Rev. 1.00 Oct. 01, 2007 Page 179 of 1956
REJ09B0256-0100