SH7763 Datasheet, PDF (341/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Function
Description
17
USBH
0
R
16
GETHER 0
R
15
PCC
14, 13 —
0
R
All 0
R
12
ADC
0
R
Indicates USBH interrupt
Indicates interrupt
source
sources for each
Indicates GETHER interrupt
source
peripheral module
(INT2A11 is affected
by the state of the
Indicates PCC interrupt source _{interrupt mask}
These bits are always read as ^register).
0. The write value should
always be 0.
0: No interrupts
1: Interrupts are
Indicates ADC interrupt source _generated
11
TPU
0
10
SIM
0
9
SIOF2 0
8
SIOF1 0
7
LCDC
0
R
Indicates TPU interrupt source Note: Reading the
R
Indicates SIM interrupt source
INTEVT code
notified to the
R
Indicates SIOF2 interrupt
CPU directly can
source
identify interrupt
R
Indicates SIOF1 interrupt
source
R
Indicates LCDC interrupt
source
sources. In this
case, reading
INT2A11 is not
necessary.
6
—
0
R
This bit is always read as 0.
The write value should always
be 0.
5
IIC1
0
R
Indicates IIC1 interrupt source
4
IIC0
0
R
Indicates IIC0 interrupt source
3
SSI3
0
R
Indicates SSI3 interrupt source
2
SSI2
0
R
Indicates SSI2 interrupt source
1
SSI1
0
R
Indicates SSI1 interrupt source
0
SECURITY* 0
R
Indicates SECURITY interrupt
source
Note: * This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 275 of 1956
REJ09B0256-0100