SH7763 Datasheet, PDF (401/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Bit
Bit Name
31 to 16 
Initial
Value
All 0
15 to 3 
All 0
2 to 0 AREASEL 000
R/W
R/W
R
R/W
Description
Reserved
Set these bits to H'A5A5 only when writing to AREASEL
bits in this register.
These bits are always read as 0.
Reserved
These bits are always read as 0. The write value should
always be 0.
DDRIF/PCIC Memory Space Select
000: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the
DDRIF space and other areas as the LBSC space
001: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the
DDRIF space, area 4 (H'1000 0000 to H'13FF FFFF) as
the PCI memory space, and other areas as the LBSC
space
010: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF) as the
DDRIF space and other areas as the LBSC space
011: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF) as the
DDRIF space, area 4 (H'1000 0000 to H'13FF FFFF) as
PCI memory space, and other areas as the LBSC space
100: Sets areas 2 to 5 (H'0800 0000 to H'17FF FFFF) as the
DDRIF space
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
The MMSELR must be written by the CPU. Writing to MMSELR, DMAC and PCIC module
should be set not to access this register, and all processing in execution should be finished, for
example execute SYNCO instruction preceding MOV instruction, and then modify MMSELR.
And execute twice MOV instruction of read out MMSELR (dummy read) and SYNCO instruction
in succession immediately after MOV instruction of write to MMSELR.
Rev. 1.00 Oct. 01, 2007 Page 335 of 1956
REJ09B0256-0100